In a semiconductor test apparatus which tests a semiconductor component such as an IC or an LSI as a device under test (DUT), a predetermined test pattern is applied to the DUT, an output signal which is output from the DUT as a result of test pattern application is fetched with a timing of a predetermined strobe signal, and the fetched output signal is compared with a predetermined expected signal (an expected pattern) to determine the quality of an operation of the DUT (see, e.g., Japanese Patent Application Laid-open No. 110357-1995: pp. 4–6, FIG. 1, Japanese Patent Application Laid-open No. 174827-1995: pp. 4–5, FIG. 1, and Japanese Patent Application Laid-open No. 062292-1996: pp. 3–4, FIG. 1).
Test pattern data applied to the DUT comprises waveform data (format control data) indicative of a waveform corresponding to a logical pattern and timing data (timing set data) indicative of a timing of an edge in this waveform, arbitrary waveform data and timing data are selected from a plurality of sets of waveform data and timing data, thereby generating a desired test pattern.
Here, in order to highly accurately evaluate characteristics of the DUT, generation of a test pattern with a highly accurate timing is demanded in recent semiconductor test apparatuses, and it is often the case that a timing set in the test pattern (a delay time of an edge with respect to a predetermined reference of a test cycle) is a sum of an integral multiple of a reference clock (Reference Clock: REFCLK) and a fraction or only an integral multiple of the reference clock. Therefore, timing data (delay data) indicative of an edge timing of waveform data is also constituted by a combination of integral multiple data (Gate Enable: GTE) of a reference clock cycle and high resolution data (High Resolution: HR) as fractional data of the reference clock.
Further, in recent semiconductor test apparatuses, combinations of a plurality of sets of waveform data are usually utilized so that further complicated test patterns can be generated.
For example, a plurality of groups (a group of set signals: T1S, T2S . . . TnS, a group of reset signals: T1R, T2R . . . T2R) are prepared as waveform data, and a timing pulse is generated by arbitrarily combining the set signals and the reset signals.
Further, such set signals and reset signals are supplied to a flip-flop, and a rising edge or a falling edge of a test pattern is formed.
FIG. 6 is a block diagram showing a schematic structure of a conventional semiconductor test apparatus.
As shown in this drawing, the conventional semiconductor test apparatus comprises a pattern generator (PG) 110, timing generators 120, a waveform memory 130, a real time selector 140 and others, a plurality of sets of waveform data output from the waveform memory 130 and a plurality of sets of timing data output from the timing generator are selected by the real time selector 140, and a test pattern input to a DUT (not shown) as a device under test is generated.
Of these components, the waveform memory 130 and elements on the next stage constitute a waveform formatter circuit.
It is to be noted that the semiconductor test apparatus shown in FIG. 6 is a pin multiplex mode tester using two sets of data in one test cycle, waveform data of groups T1 and T2 are generated from the waveform memory 130, and two timing generators 120 of T1 and T2 are provided in accordance with the groups of the waveform data from the waveform memory 130.
The pin multiplex mode is a mode in which a high-speed test signal or strobe signal is generated by combining (multiplexing) test patterns or strobe signals generated from a plurality of test channels (tester pins) of the semiconductor test apparatus on a time base.
The PG 110 outputs pattern data (PAT A/B/C) which becomes an address of a logical pattern (waveform data) which is applied to a DUT, a timing set (TS) which becomes an address of timing data indicative of a switching timing for the pattern data, and a rate signal which serves as a test rate.
The plurality of timing generators 120 are provided in accordance with the groups of the waveform data from the waveform memory 130, the two timing generators of T1 and T2 are provided in the example shown in FIG. 6, and each timing generator 120 comprises a timing memory 121 and a counter delay 122.
The timing memory 121 stores a delay timing of a clock with respect to a timing set, and generates a set time and a reset time of waveform data read from the waveform memory 130.
Specifically, the timing memory 121 stores a GATE signal used to select any clock of reference clocks REFCLK and an HR signal which is high-resolution delay data which is not more than a cycle of this REFCLK, and the reference clock REFCLK corresponds to 4 ns in the example shown in FIG. 6.
Further, the GATE signal and the HR signal are read with a timing set (TS) output from the PG 110 being used as an address, the HR signal is input to a real time selector 140 on the next stage as it is, and the GATE signal is output with a timing of a rate signal (RATE) input to the counter delay 122 and then input to the real time selector 140.
The waveform memory 130 stores waveform data (a SET/RES beat) corresponding to a logical pattern. Furthermore, respective waveform data of a set time and a reset time are read from the waveform memory 130 with pattern data (PAT A/B/C) output from the PG 110 being used as addresses.
In the waveform memory 130 shown in FIG. 6, respective waveform data of a set time and a reset time of pattern data in two groups (T1, T2) are output and then input to the real time selector 140 on the next stage.
The waveform memory 130 has, e.g., eight words, and a word is specified by three bits (A/B/C) of the pattern data (PAT). Data such as driver high-level drive first data T1S, driver low-level drive first data T1R, driver high-level drive second data T2S and driver low-level drive second data T2R is read every time each word is read.
It is to be noted that, as to a storage content of this waveform memory 130, it differs depending on a type of waveform to be generated, i.e., whether a non-return waveform NRZ, its inverse waveform/NRZ, a return waveform RZ, its inverse waveform/RZ, an exclusive OR waveform XOR, its inverse waveform/XOR and others, and a waveform is formed in accordance with the storage content.
The real time selector 140 receives respective signals from the timing generator 120 and the waveform memory 130 on a set side (SET) and a reset side (RES), selects arbitrary data in real time, and outputs the selected data as a set signal (SET) and a reset signal (RES).
The set signal (SET) and the reset signal (RES) output from the real time selector 140 are distributed to a set side and a reset side of a timing circuit (Pin Timing Generator: PTGA) 160 on the next stage. In the example shown in FIG. 6, an upper timing circuit (PTGA) 160a is a set signal passage (path) and a lower timing circuit (PTGA) 160b is a reset signal passage (path).
Moreover, the set signal and the reset signal are supplied to a flip flop 170, and a rising edge or a falling edge of a test signal are formed based on timings of these signals.
In the semiconductor test apparatus having the above-described structure, when a pattern is started, signals from the PG 110 access the waveform memory 130 and the timing memory 121, and outputs from these members are input to the real time selector 140.
Specifically, when a pattern is started, timing data TS and a rate signal RATE are supplied to the timing memory 121 and the counter delay 122 from the PG 110, and a delay quantity HR and a reference timing GTE read from the timing memory 121 are output.
Additionally, waveform data is read from the waveform memory 130 by using pattern data PAT from the PG 110, input to the real time selector 140 with a timing of the reference timing GTE, and selected and output with a delay timing of the delay quantity HR.
Further, this data is applied to a non-illustrated DUT through the timing circuit (PTGA) 160 and the flip flop 170.
Meanwhile, generally, in the semiconductor test apparatus, an interval between signals which are supplied to the same signal passage must be larger than that of a reference clock. For example, each of an interval between two set signals in the signal passage on the set side 160a of the timing circuit (PTGA) 160 and an interval between two reset signals in the signal passage on the reset side 160b of the same shown in FIG. 6 must be larger than a reference clock cycle. That is because each functional element, each circuit or the like is configured to operate in synchronization with a reference clock in the semiconductor test apparatus, a signal having a smaller cycle than the cycle of the reference clock cannot be recognized, and such a signal cannot be correctly transmitted.
As described above, in the semiconductor test apparatus, when a high-speed pulse exceeding a limit of the reference clock REFCLK is applied, a normal operation cannot be carried out. Here, within the context of the background art and the present invention, such a limit is referred to as a “proximity limit”. Typically, a proximity limit time is a time length of one cycle of the reference clock.
Therefore, when HR signals each indicating a delay timing of a high resolution are continuously applied in a cycle not longer than that of the reference clock REFCLK, the PTGA cannot differentiate and recognize the second pulse, and it responds to a smaller HR signal as though one continuous pulse were applied.
Thus, in the prior art, a signal which conflicts with a proximity limit of a clock of the PTGA 160 on the later stage is eliminated in advance so that such a signal cannot be output in the real time selector 140 (see, e.g., Japanese Patent Application Laid-open No. 094722-1996: pp. 2–3, FIG. 1, and Japanese Patent Application Laid-open No. 228721–2002: pp. 4–5, FIG. 1)
Specifically, if the same reference clock cycle has one waveform data edge, the real time selector 140 selects and outputs this edge and the corresponding timing data. If the same reference clock cycle has a plurality of waveform data edges, the real time selector 140 compares the sets of timing data associated with the respective edges, and selects and outputs an edge having small timing data and this timing data. Furthermore, as to edge data having large timing data, the real time selector 40 opens (inhibits) this edge data so that this data cannot be output. It should be noted that within the context of the background art and the present invention, a term “open” is used for describing a situation where a signal or data is inhibited or prohibited to be transmitted to later stages.
Based on this, in any case, a signal which is proximate to or exceeds the proximity limit time derived from a reference clock cycle (e.g., 4 ns) is not input to the PTGA.
A concrete example of a test pattern generated in the conventional semiconductor test apparatus will now be described with reference to FIG. 7.
FIG. 7 shows a timing chart of a test pattern generated in the above-described conventional semiconductor test apparatus. In the example shown in this drawing, a reference clock REFCLK is 4 ns, and a test rate RATE is set to 4 ns which is the same as the reference clock.
It is to be noted that the reference clock REFCLK remains unchanged (fixed) by its semiconductor test apparatus, but the test rate RATE can be set to a desired cycle which is an integral multiple of the reference clock REFCLK, and this setting can be arbitrarily performed by a user or the like.
As shown in this drawing, respective sets of waveform data T1S, T1R, T2S and T2R are input to the set side (SET) and the reset side (RES) of the real time selector 140 with a timing of the reference timing GTE. Moreover, delay timing data T1HR and T2HR corresponding to the respective sets of waveform data T1 and T2 are input to the set side (SET) and the reset (RES) side of the real time selector 140.
In the real time selector 140, if the same reference clock cycle has one waveform data edge, this edge and corresponding timing data are selected and output. If the same reference clock cycle has a plurality of waveform data edges, respective sets of timing data corresponding to the respective edges are compared with each other, and an edge having small timing data and this timing data are selected and output.
Additionally, as to an edge having large timing data, this edge data is opened so that it cannot be output.
In the example shown in FIG. 7, in the first cycle of the reference clock cycle, since the SET signal is T1S only, T1S is selected, and the SET signal is output with a delay timing of 0.5 ns indicated by T1HR.
In the second cycle of the reference clock cycle, since the RES signal is T1R only, T1R is selected, and the RES signal is output with a delay timing of 1.0 ns indicated by T1HR.
In the third cycle of the reference clock cycle, since both T1S nd T2S exist as the set signal, values of the delay timing data T1HR (0.5 ns) and T2HR (3.0 ns) corresponding to the respective sets of waveform data are compared with each other, T1S having a smaller value is selected, and the SET signal is output with a delay timing of 0.5 ns indicated by T1HR. In this third cycle, T2S having large delay timing data is opened and erased (see SET 3.0 indicated by an upward broken arrow in FIG. 7), and it is not output from the real time selector 140. In other words, the set signal (edge) T2S is inhibited to be transferred to the later stages.
Thereafter, the waveform data and the timing data are likewise selected in accordance with each cycle, and the set signal (SET) and the reset signal (RESET) such as shown in FIG. 7 are output from the real time selector 140. Further, these set signal and reset signal are supplied to the timing circuit (PTGA) 160 and the flip flop 170, and a test pattern (PAT) having such a rising edge or falling edge as shown in the lowermost column in FIG. 7 is generated.
In this manner, by opening (inhibiting) a clock which conflicts with a proximity limit in the real time selector 140, namely, a clock which is proximate to or exceeds a reference clock cycle (e.g., 4 ns) is not input to the PTGA on the later stage, and hence the semiconductor test can be accurately conducted based on the reference clock.
In the above-described conventional semiconductor test apparatus, however, data of an edge timing which conflicts with the limit is opened and erased by the proximity limit of the clock, which results in a problem that an output waveform varies due to opening the edge when the timing setting is changed by a user.
For example, as shown in FIG. 8(a), it is assumed that the set signal and the reset signal are output with a timing which does not conflict with the proximity limit. In this case, it is assumed that the timing setting is changed by a user or the like so that a delay timing of SET=1.0 ns of the first cycle shown in FIG. 8(a) is changed to SET=2.0 ns.
Then, as shown in FIG. 8(b), since SET=2.0 ns of the second cycle conflicts with the proximity limit of 4 ns with respect to SET=2.0 ns of the first cycle, SET=2.0 ns of the second cycle is opened. As a result, an output waveform is changed to a waveform which is different from the correct waveform shown in FIG. 8(a).
Even in such a case, however, if an edge of RES=3.0 ns does not exist before the opened edge shown in FIG. 8(b), the subsequent output waveform is not changed even if SET=2.0 ns of the second cycle is opened.
As described above, when a given edge conflicts with the proximity limit of the clock and is thereby opened, there are a case where the subsequent output waveform is changed due to this opening and another case where the output waveform is not changed and hence there is actually no impact.
In the conventional semiconductor test apparatus, however, when the clock is opened, the fact that the clock is opened can be detected. However, the conventional apparatus cannot detect a difference between opening which affects the above-described output waveform and opening which does not affect the same.
Therefore, there is a problem that opening of the edge which is truly required for correct waveform generation cannot be accurately detected.